The present invention relates generally to semiconductor devices, and more particularly, to techniques for analyzing and debugging circuitry within an integrated circuit die.
The semiconductor industry has recently experienced technological advances that have permitted dramatic increases in circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors, operating at speeds of hundreds of millions of instructions per second to be packaged in relatively small, air-cooled semiconductor device packages. A by-product of such high-density and high functionality in semiconductor devices has been the demand for increased numbers of external electrical connections to be present on the exterior of the die and on the exterior of the semiconductor packages which receive the die, for connecting the packaged device to external systems, such as a printed circuit board.
As the manufacturing processes for semiconductor devices and integrated circuits increase in difficulty, methods for testing and debugging these devices become increasingly important. Not only is it important to ensure that individual chips are functional, it is also important to ensure that batches of chips perform consistently. In addition, the ability to detect a defective manufacturing process early is helpful for reducing the number of defective devices manufactured.
Traditionally, integrated circuits have been tested using methods including directly accessing circuitry or devices within the integrated circuit. In addition, many methods require the circuit to be powered. Directly accessing the circuitry is difficult for several reasons. For instance, in flip-chip type devices, transistors and other circuitry are located in a very thin epitaxially-grown silicon layer in a circuit side of the die. The circuit side of the die is arranged face-down on a package substrate. This orientation provides many operational advantages. However, due to the face-down orientation of the circuit side of the die, the transistors and other circuitry near the circuit side are not readily accessible for testing, modification, or other purposes. Therefore, access to the transistors and circuitry near the circuit side is from the back side of the chip.
Since access to the transistors and circuitry in flip-chips is generally from the back side of the device, it is often necessary to mill through the back side and probe certain circuit elements in order to test the device. Often, the area between transistors and other circuitry in flip-chip and other integrated circuit dies is very small. Probing points between such circuitry and devices is difficult to achieve without contacting the devices between which the probes are formed and potentially causing damage. This difficulty inhibits the access and probing of circuit areas located between and beneath such circuitry.
The present invention is directed to a method and system for improving post-manufacturing analysis of a semiconductor device involving providing access to hard-to-reach portions of the circuitry. The present invention is exemplified in a number of implementations and applications, some of which are summarized below.
According to an example embodiment of the present invention, an elongated narrow conductive via probe is formed in a semiconductor device having circuitry in a circuit side opposite a back side. The probe is formed by first removing substrate from the semiconductor device and forming an exposed region over a target node between circuitry in the device. A conductor is formed for accessing the target node and extending between the circuitry and into the back side, and is used for analyzing the device. By forming the conductor between circuitry in the device, access to the target node is facilitated.
According to another example embodiment of the present invention, a system is arranged for forming an elongated narrow conductive via probe for analyzing a semiconductor device having circuitry in a circuit side opposite a back side. The system includes a substrate removal device that is adapted to remove substrate from the back side and to form an exposed region over a target node between circuitry. An ion deposition device is also included and is adapted to form a conductor for coupling to and accessing the target node and extending between the circuitry and into the back side. A testing arrangement is adapted to use the formed conductor and to analyze the device.
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The FIGS. and detailed description which follow more particularly exemplify these embodiments.